1. Field of the Invention
The present invention relates to a power-on reset circuit for generating a reset signal for initializing a system while being connected to a power source.
2. Related Art
As a conventional power-on reset circuit, there is a known one disclosed in Japanese Patent Kokai No.10-163840, for example. FIGS. 1A and 1B there in are diagrams explaining the power-on reset circuit. FIG. 1A shows a circuit configuration whereas FIG. 1B shows operation waveforms.
As shown in FIG. 1A, the power-on reset circuit includes N-channel MOS transistors 1, 2 (hereinafter, a MOS transistor will be referred to simply as MOS while an N-channel MOS will be referred to simply as NMOS) which are connected in series between a node NA and a ground potential GND. The NMOS s 1, 2 each have its gate connected to a power supply line 10 so as to be supplied with a power supply voltage VD. Connected between the node NA and the power supply line 10 is a MOS capacitor 3 utilizing capacitance between the gate and source/drain of a P-channel MOS (hereinafter, referred to as PMOS) Specifically, the gate of the PMOS is connected to the node NA whereas the source and drain thereof are connected to the power supply line 10.
On the other hand, the node NA is connected with an input of an inverter 4, the output of which is connected with a node NB. Connected between the node NB and a ground potential GND is a MOS capacitor 5 utilizing capacitance between the gate and source/drain of an NMOS. Specifically, the gate of the NMOS is connected to the node NB whereas the source and drain thereof are connected to a ground potential GND.
The node NB is further connected with inverters 6, 7 in cascade. A reset signal POR is outputted from the inverter 7 and applied to the circuit block to be reset. Although not shown in the figure, an arrangement is made such that the power supply voltage VD power source is supplied to the inverters 4, 6, 7 and the circuit block via the power supply line 10.
Next, operations of the power-on reset circuit will be described.
Prior to the power-on transition, the power supply voltage VD is at 0V and hence, the nodes NA, NB are at the ground potential GND so that the MOS capacitors 3, 5 store no electric charges. Therefore, the MOS capacitors 3, 5 each have a terminal-to-terminal voltage of 0V. When the power is applied at time t0 as shown in FIG. 1B, the power supply voltage VD on the power supply line 10 starts rising from 0V to a predetermined power supply potential VDD.
Immediately after the power is turned on, when the power supply voltage VD is below the threshold voltage VTN of the NMOS s 1, 2, these NMOS s 1, 2 are OFF and the node NA is connected to the power supply line 10 via the MOS capacitor 3 whose terminal-to-terminal voltage is 0V. Hence, by charge conservation, the potential VA of the node NA will be increased in the same manner as the power supply voltage VD.
At time t1 when the power supply voltage VD exceeds the threshold voltage VTN, the NMOSs 1, 2 have their gates connected to the power supply line 10 and so are turned ON. This permits a current to flow from the node NA to the ground potential GND via the NMOSs 1, 2. Accordingly, the subsequent fluctuation of the potential VA is greatly affected by the rate of increase of the power supply voltage VD, the on resistance (drive current capability) of the NMOSs 1, 2 and the capacity of the MOS capacitor 3. That is, if the power supply voltage VD rises fast, the MOS capacitor 3 has a large capacity and the NMOSs 1, 2 has large on resistances, the increase of potential VA follows closely the increase in the power supply voltage VD, albeit at a lower rate.
From time t2 when the power supply voltage VD reaches the predetermined power supply potential VDD, the potential VA exponentially falls in accordance with the time constant of the on resistance of the NMOSs 1, 2 and the time constants of the capacitance of NMOS 3.
At time t3 when the potential VA of the node NA decreases below ½ of the power supply voltage VD, the output signal from the inverter 4 connected with the node NA is shifted from L level to H level. Since the MOS capacitor 5 is connected between the node NB on the output side of the inverter 4 and the ground potential GND, the potential VB of the node NB rises from the ground potential GND to the power supply potential VDD in accordance with a given time constant.
At time t4 when the potential VB of the node NB rises to above ½ of the power supply voltage VD, the output from the inverter 6 connected with the node NB is inverted and the output from the inverter 7 connected in cascade with the inverter 6 is also inverted, thereafter applied as the reset signal POR to the circuit block.
However, the aforesaid power-on reset circuit has the preconditions that the power supply voltage VD rises fast, the MOS capacitor 3 has large capacity, and the on resistances of the NMOSs 1, 2 are large, so that the potential VA of the node NA continues to rise after the NMOSs 1, 2 are turned ON.
Hence, the following problem may be encountered in the following case. If when the power is turned on, the rise of the power supply voltage VD is slow, the potential VA of the node NA may rise very little or even start falling after the NMOSs 1, 2 are turned ON. In such cases, the node NA stays at L level from the start and remains unchanged, whereas the node NB stays at H level and remains unchanged. Therefore, the reset signal POR assumes H level from the start, disabling normal resetting operations.
To cope with this slow rise of the power supply voltage VD without changing circuit configuration, the gate lengths of the NMOSs 1, 2 need to be increased so as to increase the on resistances thereof, or to increase the gate area of the PMOS gate so as to increase the capacity of the MOS capacitor 3. This results in an undesirable increase in area of the circuit pattern.
It is an object of the invention to provide a power-on reset circuit capable of outputting a normal reset signal POR despite the slow rise of the power supply voltage VD.